Astera Labs has expanded its Leo Smart Memory Controller family with three new memory connectivity products designed to address rapidly increasing memory requirements across agentic AI, cloud infrastructure, and other data-intensive workloads.
The semiconductor connectivity company introduced the Leo X-Series alongside the Leo 2 E-Series and Leo 2 P-Series, extending the platform across direct fabric-attached GPU memory, CPU-attached memory expansion and pooled or shared rack-scale memory architectures.
The launch comes as larger AI context windows, persistent agent sessions and increasingly sophisticated inference workloads place greater pressure on data center memory capacity and bandwidth.
Astera Labs is targeting that problem from multiple directions: placing additional memory closer to AI accelerators, increasing CPU-accessible capacity, pooling unused memory across servers and allowing infrastructure operators to reuse previously deployed DDR4 DIMMs alongside newer DDR5 systems.
The company said the new Leo products are already generating increased design activity and design wins across AI labs, hyperscalers and neocloud providers.
Leo X-Series Targets Agentic AI And KV Cache
The new Leo X-Series is designed specifically for fabric-attached memory serving AI accelerators.
Paired with Astera Labs’ Scorpio X-Series Fabric Switches, Leo X-Series can create a dedicated memory tier for AI workloads that need to store large amounts of KV cache and agent context.
KV cache, or key-value cache, is temporary memory used by large language models to retain information generated while processing previous tokens.
The technique allows a model to avoid repeatedly recalculating earlier portions of a conversation or context window.
As AI applications support longer conversations and more persistent agent interactions, the amount of information stored in KV cache can grow substantially.
That creates both capacity and performance challenges.
If the required memory is too far from the GPU or cannot deliver sufficient bandwidth, inference can slow even when the underlying accelerator has available computing capability.
Astera Labs’ architecture attempts to address that bottleneck by connecting memory directly to the scale-up fabric used by AI accelerators.
Leo X-Series supports PCIe as well as platform-specific protocols, allowing hyperscalers and AI infrastructure companies to develop customized memory architectures around their preferred compute platforms.
Astera Labs said the architecture can provide a lower-latency, higher-bandwidth path between GPUs and KV cache than designs relying entirely on CPU-attached memory or NVMe storage.
In the company’s internal testing, the approach delivered up to 62% lower time to first token and up to 22% more tokens per second.
The benchmark used an Intel Granite Rapids server with eight populated DDR5 memory channels, a data center Gen 5 AI accelerator and the Qwen2.5-32B model.
Those metrics are increasingly important to what infrastructure providers describe as token economics.
AI inference economics are determined not only by the price and performance of GPUs but by how effectively the surrounding infrastructure keeps those accelerators supplied with data.
A GPU waiting for data from a slower storage or memory tier represents expensive capacity that is not being fully utilized.
By creating another high-speed memory tier near the accelerator fabric, Astera Labs is attempting to let customers increase effective AI system performance without simply adding more GPUs.
Leo 2 E-Series Expands CPU Memory Capacity
Astera Labs is addressing a different part of the memory problem with the enhanced Leo 2 E-Series.
The E-Series connects additional memory directly to CPUs through CXL 3.2 and PCIe 6 x16 connectivity.
This allows infrastructure providers to increase the amount of memory available to a server without adding another CPU socket.
The new generation incorporates four DDR4 or DDR5 memory controllers and doubles both memory bandwidth and capacity compared with the previous generation.
Astera Labs has also optimized the chip package for add-in cards and other dense DIMM configurations.
The architecture can support AI agents, in-memory databases and conventional cloud workloads that require substantial memory capacity but do not necessarily need all of that memory placed directly next to GPUs.
The E-Series also enables operators to reuse previously deployed memory in newer cloud servers.
That capability is becoming more significant as demand for AI infrastructure contributes to tighter memory availability and higher costs.
Instead of retiring older DDR4 DIMMs when deploying a newer server generation, cloud operators could potentially redeploy part of that capacity through Leo-based expansion architectures.
Astera Labs sees memory reuse as one way to improve infrastructure economics during a period when organizations are simultaneously building new AI clusters and refreshing large fleets of traditional cloud servers.
Leo 2 P-Series Pools Memory Across Servers
The Leo 2 P-Series goes a step further by allowing memory to be pooled and shared across multiple hosts.
The product supports dual-port PCIe 6 x8 connectivity and CXL-based dynamic capacity management.
Rather than installing enough memory in every individual server to handle that machine’s possible peak demand, operators can create a shared pool from which hosts draw capacity as needed.
That could improve utilization across large data center environments.
Traditional server architectures can leave substantial amounts of DRAM stranded inside systems that are not fully using their installed capacity.
At the same time, other servers may need additional memory.
Pooling creates the potential to treat memory more like a rack-level resource rather than something permanently assigned to one machine.
Astera Labs believes that becomes particularly valuable when memory supply is constrained because customers can extract more useful capacity from DRAM they have already purchased.
The company is positioning the E-Series and P-Series as complementary products.
E-Series provides straightforward memory expansion for an individual CPU host.
P-Series enables a more disaggregated architecture where memory resources can be dynamically distributed across several systems.
Together with Leo X-Series, the expanded portfolio gives Astera Labs products spanning accelerator-attached, CPU-attached and pooled memory.
Memory Reuse Becomes Part Of AI Infrastructure Economics
Astera Labs is also emphasizing reliability and lifecycle management as customers begin combining older and newer memory technologies inside the same infrastructure.
The Leo family includes hyperscale-grade reliability, availability and serviceability capabilities alongside memory-health management.
Purpose-built test engines can examine DIMMs before deployment, while automated repair engines are intended to identify memory suitable for continued use.
The products also support enhanced error reporting, event logging, memory scrubbing, thermal management and resilient firmware updates.
Additional capabilities include workload monitoring, performance profiling, hotness tracking, software-defined data placement and latency optimization.
Astera Labs combines those capabilities with its COSMOS software suite to provide broader fleet-level visibility across DDR4, DDR5, pooled and accelerator-attached memory.
That management layer becomes more important as memory architectures become increasingly disaggregated.
A traditional server might have a relatively straightforward relationship between a CPU and the DIMMs physically installed beside it.
Modern AI infrastructure can include local accelerator memory, CPU memory, pooled CXL memory, fabric-attached capacity and storage-based memory tiers.
Determining where data should reside at any moment becomes a systems optimization problem.
Astera Labs is attempting to provide both the semiconductor connectivity and management software needed to coordinate those increasingly complicated memory environments.
Agentic AI Drives Growing Memory Requirements
The broader driver behind the launch is the shift toward agentic AI.
AI agents can maintain longer histories, interact with multiple systems and operate across extended sessions.
That means an agent may need to preserve far more context than a conventional short chatbot interaction.
Every additional token retained can contribute to larger KV-cache requirements.
The challenge compounds when thousands or millions of concurrent users interact with agents operating on the same infrastructure.
Astera Labs argues that memory provisioning is therefore becoming one of the central economic constraints in AI inference.
Matt Kimball of Moor Insights & Strategy said agentic AI adoption is growing faster than the industry’s ability to provision memory, at the same time DDR5 supply remains tight and pricing is increasing.
The result is additional pressure on data center operators to use existing memory more efficiently rather than solving every capacity problem by purchasing more DRAM.
For Astera Labs, that creates an opportunity extending beyond traditional connectivity chips.
The company has positioned itself around rack-scale AI infrastructure, developing semiconductor and software technologies that connect processors, accelerators, memory and networks.
Its Intelligent Connectivity Platform incorporates CXL, Ethernet, NVLink Fusion, PCIe and UALink technologies together with COSMOS software.
The company also develops custom connectivity products for customers requiring architectures beyond its standards-based portfolio.
The expanded Leo family extends that strategy further into memory management.
AMD, Arm, Intel And Samsung Support Expanded Leo Platform
Astera Labs developed the enhanced Leo portfolio in collaboration with major CPU, GPU and memory ecosystem partners.
The company specifically identified AMD, Arm and Intel along with major memory suppliers and additional hyperscale and original equipment manufacturer collaborators.
The new products are currently sampling with hyperscaler customers.
AMD sees CXL memory expansion as complementary to its EPYC server processors as AI and cloud workloads require increasing amounts of memory.
Arm is working with Astera Labs to pair its AGI CPU technology with Leo CXL Smart Memory Controllers for agentic AI, reinforcement learning and database workloads.
Intel similarly views CXL as a way to make data center memory more flexible and efficient.
Samsung Electronics is collaborating with Astera Labs around CXL memory solutions intended to improve interoperability and support scalable memory architectures for AI infrastructure.
The ecosystem support is significant because next-generation memory architectures depend on interoperability across CPUs, accelerators, switches, controllers, memory modules and software.
CXL was created in part to establish standardized connectivity that lets those components share memory resources more efficiently.
Astera Labs’ role is to provide controllers and connectivity infrastructure that translate those standards into deployable rack-scale architectures.
The company will demonstrate the expanded Leo family during AI Infra Summit 2026 at the Santa Clara Convention Center from September 15 through September 17.
Demonstrations will include direct fabric-attached memory for agentic AI, DDR4 reuse, dynamic memory pooling and agentic AI memory tiering using Leo with Scorpio X-Series switches.
For Astera Labs, the launch expands its opportunity as AI infrastructure spending moves beyond accelerators themselves.
The enormous investment in GPUs is also creating demand for technologies that make those processors more efficient.
Memory, networking, switching and connectivity are increasingly important components of the overall AI system architecture.
Astera Labs is betting that memory in particular will become one of the most important bottlenecks as agentic applications expand context windows and retain increasing amounts of information.
The expanded Leo portfolio is designed to address that constraint by helping operators add capacity where it is needed, share capacity where it would otherwise remain unused and redeploy memory that might otherwise be retired.
KEY QUOTES:
“Agentic AI adoption is outpacing the industry’s ability to provision memory for it, and that gap is widening every quarter. That growth is landing at the worst possible time for memory supply, with DDR5 tight and pricing climbing, so every gigabyte already deployed has to work harder. The new Leo X-Series and Leo 2 E and P-Series Smart Memory Controllers immediately address KV-cache-intensive AI workloads, improve memory utilization, and reliably reuse previously deployed memory across both AI and general-purpose cloud infrastructure, instead of simply buying more of it.”
Matt Kimball, Vice President and Principal Analyst at Moor Insights & Strategy
“Agentic AI is where the economics of AI infrastructure are being decided, and those economics depend on putting every usable gigabyte of memory to work. The enhanced Leo family gives infrastructure providers purpose-built ways to connect memory to accelerators, CPUs, and hosts across the rack, turning previously deployed and stranded capacity into a resource that new AI and cloud workloads can use. We’re seeing that translate into broader customer engagement across AI labs, hyperscalers, and neoclouds.”
Thad Omura, Senior Vice President, Compute Connectivity Group at Astera Labs
“Agentic AI is increasing demand for balanced systems that can move and process more data without sacrificing efficiency. AMD EPYC processors deliver leadership performance, exceptional memory bandwidth and capacity, and high-speed I/O across the broadly deployed x86 platform. Our collaboration with Astera Labs around CXL extends that foundation, giving customers greater flexibility to scale memory-intensive AI and cloud workloads and improve infrastructure utilization.”
Robert Hormuth, Corporate Vice President, Architecture and Strategy at AMD
“As AI infrastructure evolves, agentic AI, reinforcement learning and database workloads are driving demand for higher-capacity memory. Arm and Astera Labs are working together to pair Arm AGI CPU with Leo CXL Smart Memory Controllers, helping customers meet these growing requirements while maintaining scalable performance.”
Eddie Ramirez, Vice President of Go-To-Market, Cloud AI at Arm
“CXL was created to bring greater flexibility and efficiency to memory across the data center. Technologies like Astera Labs’ Leo Smart Memory Controllers help turn that vision into reality, demonstrating how ecosystem innovation can help customers get more out of their AI infrastructure and support the next generation of data-intensive workloads.”
Srini Krishna, Fellow at Intel Data Center Group
“We are contributing to the evolution of AI infrastructure through the development of CXL memory solutions designed to help address the growing memory demands of modern data centers. We are excited to collaborate with Astera Labs to help ensure our DRAM solution offer strong interoperability within the evolving CXL ecosystem, and remain committed to supporting a scalable, high-performance memory architecture for the AI era.”
Jangseok Choi, Vice President of Product Planning Team at Samsung Electronics
