Qnity Electronics has introduced an integrated materials platform for advanced semiconductor packaging, combining metallization, bumping, dielectric, and fine-line patterning technologies to support increasingly complex AI and high-performance computing architectures.
The platform is designed for next-generation 2.5D, 3D and panel-level packaging, where higher interconnect density, tighter dimensional control and manufacturing yield are becoming increasingly important as chips move toward more complex vertical designs.
Qnity is targeting applications involving artificial intelligence, chiplets, high-bandwidth memory, 3D stacking and heterogeneous integration.
The company said those architectures are increasing integration complexity across semiconductor manufacturing and driving greater demand for coordinated materials and process solutions that work across multiple package layers.
Qnity’s portfolio supports advanced packaging technologies including Chip-on-Wafer-on-Substrate, Embedded Multi-die Interconnect Bridge and high-bandwidth memory.
These architectures require precise plating height, strong coplanarity, and tight dimensional control as interconnects become smaller and chip designs incorporate more components.
The platform supports tin-silver micro-bumps as well as copper-to-copper direct and hybrid bonding.
Qnity said its dielectric and fine-line patterning technologies can enable metallization with line and space dimensions as small as 2 micrometers while maintaining tight critical dimension control and low defectivity.
One component of the platform is Intervia CB1000+ and CB3000 copper technology, designed to improve within-die uniformity, provide a broad operating window, maintain total indicated runout control, and support low-impurity copper deposition.
The company’s Solderon TS8000 series is designed for tin-silver micro-bump plating used in high-bandwidth memory applications.
The technology is intended to provide strong coplanarity across mixed-pitch and fine-pitch micro-bumps while supporting soluble and insoluble electrode plating processes.
Qnity is also introducing Riston WBR5000, a thick dry-film photoresist designed for 2.5D advanced packaging.
The material supports high-aspect-ratio copper pillar plating and fine-feature lithography with film thickness ranging from approximately 200 to 320 micrometers.
Another component, Cyclotene dry-film photo-imageable dielectric, is designed for fan-out panel-level packaging and advanced substrates.
Qnity said the material can achieve target thickness in a single processing step while maintaining coplanarity.
For glass-core substrates, Cyclotene can also fill through-glass vias and has demonstrated reliability for advanced packaging applications.
The broader strategy positions Qnity as a process-development and engineering partner, not solely a materials supplier.
Its teams are working with semiconductor manufacturers on integration issues extending from individual layers through chip-to-chip connections and larger system architectures.
The company sees thermal management and advanced packaging becoming increasingly interconnected as AI processors, accelerators and memory systems demand greater power density and more complex integration.
Qnity plans to provide additional details about the platform at the Heterogeneous Integration Global Summit during SEMICON Taiwan 2026 on September 1. At the event, Jason Chuang, Packaging Polymer Segment Director for Advanced Circuit & Packaging at Qnity, will present the company’s approach to next-generation semiconductor packaging.
KEY QUOTE:
“Customers are looking for system-level solutions, and that’s where Qnity shines. As AI, chiplets, high-bandwidth memory, 3D stacking, and heterogeneous integration drive a shift from 2D designs to increasingly complex vertical architectures, semiconductor manufacturers are facing new levels of integration complexity, creating demand for integrated solutions spanning advanced packaging and thermal management. Our teams serve as a design partner with end-to-end process development and engineering capabilities that help customers solve the integration complexity layer-to-layer, chip-to-chip, and scale new designs with confidence.”
Chuck Xu, President Of Interconnect Solutions At Qnity
