- Taiwan Semiconductor Mfg. Co. Ltd. (NYSE: TSM) has announced major partnerships with Marvell (NASDAQ: MRVL) and Synopsys, Inc. (NASDAQ: SNPS). These are the details about the deals.
Taiwan Semiconductor Mfg. Co. Ltd. (NYSE: TSM) has announced a partnership with Marvell (NASDAQ: MRVL) and Synopsys, Inc. (NASDAQ: SNPS). Marvell Technology Group Ltd. is known for engaging in the design, development, and sale of integrated circuits, which is a company that offers System-on-a-Chip devices and utilizes a technology portfolio of intellectual property in the areas of analog, mixed-signal, digital signal processing, and embedded and standalone integrated circuits. And Synopsys is known for engaging in the provision of software products and consulting services in the electronic design automation industry.
Marvell Partnership
Marvell and Taiwan Semiconductor (TSMC) recently announced an extension of their long term partnership to deliver a comprehensive silicon portfolio for the data infrastructure market utilizing the industry’s most advanced 5-nanometer (nm) process technology. And next-generation infrastructure has never been more critical to the global economy as it is what’s keeping the world connected, businesses running and information flowing.
Through this collaboration, Marvell and TSMC are advancing the essential technology underpinning this infrastructure to provide the storage, bandwidth, speed, and intelligence that tomorrow’s digital economy demands with the added customer benefit of significant energy efficiency. Built through a partnership with TSMC on the most advanced process technology currently in volume production, Marvell’s new 5nm portfolio will enable leading-edge silicon innovation for the infrastructure market.
Marvell’s 5nm portfolio will provide the essential high-performance compute, networking, and security technology required to advance infrastructure development for a multitude of end-market applications. And Marvell’s Ethernet connectivity solutions enable high-performance, low-power network connectivity, optimized for applications that span cloud data centers to the harsh environment of the automotive market.
The Marvell OCTEON platform is the industry’s leading Arm-based high-performance compute architecture for embedded infrastructure applications targeting a wide variety of wired and wireless networking equipment including switches, routers, secure gateways, firewalls, and network monitoring solutions. And OCTEON is the world’s most widely deployed data processing unit (DPU) for data-center scale computing and enables a multitude of acceleration and offload capabilities, including Smart NICs and security accelerators. With optimized and customized 5G processing and baseband capabilities, Marvell’s OCTEON Fusion platform pushes the boundaries of wireless network infrastructure.
Marvell — which has multiple designs already under contract for its 5nm portfolio — is developing solutions across the carrier, enterprise, automotive, and data center markets with first products sampling by the end of next year. And this marks a significant milestone for the infrastructure industry as the process node cadence now closely follows that of the consumer and high-performance market. The joint development positions Marvell for multi-generational leadership in data infrastructure technology. And these advanced systems based on Marvell’s leading technology platform will raise the bar for power and performance for the industry.
Marvell’s entire 5nm solution is backed by the company’s industry-leading IP portfolio that covers the full spectrum of infrastructure requirements including high-speed SerDes up to 112Gbps long-reach, processor subsystems, encryption engines, system-on-chip fabrics, chip-to-chip interconnects, and a variety of physical layer interfaces. And these technologies and more are all in development now on TSMC’s N5P process, an enhanced version of TSMC’s 5nm technology which delivers approximately 20% faster speed or 40% power reduction compared to the previous 7nm generation. This rich partnership between the two companies extends beyond 5nm to provide a reliable and long-term roadmap for Marvell’s customers.
Synopsys Partnership
Synopsys recently announced that TSMC has certified Synopsys’ digital and custom design platforms for TSMC’s 3-nanometer (nm) process technology. This certification — based on TSMC’s latest design rule manual (DRM) and process design kits (PDKs) — is the result of an extensive collaboration with rigorous validation to deliver design solutions for optimized power, performance, and area (PPA), which accelerate the path to next-generation designs.
Through a close collaboration with TSMC, Synopsys developed key enablement features and new technologies to ensure full-flow correlation from synthesis to place-and-route to timing and physical signoff for TSMC’s N3 processes. Synopsys’ Fusion Compiler RTL-to-GDSII solution and IC Compiler II place-and-route solution have been enabled with extended support of TSMC’s N3 process. Synopsys’ Design Compiler NXT synthesis solution has been enhanced to enable designers to take full advantage of TSMC’s 3nm technology, delivering improved quality of results (QoR) and tighter correlation to Synopsys’ IC Compiler II place-and-route solution using a new and highly accurate approach to resistance and capacitance estimation.
The PrimeTime signoff solution supports the advanced multi-input switching (MIS) for accurate timing analysis and signoff closure. And Design Compiler NXT is enabled for TSMC N3 process for both HPC and mobile designs. In order to optimize some of the special features with the TSMC 3nm process technology, the Synopsys digital design platform has been enhanced to support pin density aware placement and global route modeling for better routing convergence on standard cell pins, concurrent legalization and optimization (CLO) for faster timing convergence, a new cell map (cell density) infrastructure for maximizing the available white space to improve PPA, interconnect optimization by auto-generating via pillar structures and partial parallel routing for HPC design, and power-aware mixed driving strength multi-bit flip flop optimization for low-power designs.
With the Synopsys custom design platform, Custom Compiler has been enhanced to accelerate the implementation of 3nm analog designs. And these enhancements – co-developed with and validated by early 3nm users, including the Synopsys DesignWare IP team – reduce the effort to meet new design rules and other 3nm technology requirements. The Synopsys HSPICE, FineSim and CustomSim simulation solutions deliver enhanced turnaround time for TSMC 3nm designs and provide signoff coverage for TSMC 3nm circuit simulation and reliability requirements.
KEY QUOTES ON MARVELL PARTNERSHIP
“We are proud to partner with Marvell to serve the data infrastructure market with cutting-edge silicon, and are committed to supporting their growing needs in development, quality, supply and capacity. In the 5G era, more applications than ever are demanding the most advanced silicon technology we can provide. We look forward to collaborating with Marvell to meet these demands with our combined design and process expertise and extend our long history of partnership to the 5nm generation and beyond.”
— Dr. Kevin Zhang, Senior Vice President of Business Development at TSMC
“Now is the time to invest in data infrastructure – the world is relying on us – and our customers are depending on us. TSMC’s 5nm process provides world-class power, performance and gate density – and it’s critical for the demands of the leading companies in the world in cloud, 5G, enterprise, and automotive. We’re thrilled to have a strategic partner like TSMC to help us continue to push the boundaries of innovation possibilities.”
— Raghib Hussain, Chief Strategy Officer and Executive Vice President of the Networking and Processors Group at Marvell
KEY QUOTES ON SYNOPSYS PARTNERSHIP
“We’re pleased with the result of our multi-year collaboration with Synopsys in delivering platform solutions on TSMC’s advanced process that help our mutual customers achieve silicon innovations benefiting from the significant power and performance boost of our 3nm process technology and quickly launch their new product innovations to market. Certification of the Synopsys design solutions enables our mutual customers’ designs to be implemented on TSMC N3 process with high confidence for optimized PPA.”
— Suk Lee, senior director of the Design Infrastructure Management Division at Taiwan Semiconductor
“Our collaboration with TSMC on highly differentiated solutions for its advanced 3nm process technology allows customers to begin designing their increasingly complex SoCs with greater confidence. The result of our collaboration enables designers to take full advantage of the significant power, performance, and area improvements of an advanced EUV process, while accelerating the innovation for their differentiated SoCs.”
— Charles Matar, senior vice president of System Solutions and Ecosystem Enablement for the Design Group at Synopsys
