TYLsemi, a San Jose-based chiplet platform company, has emerged from stealth and closed an oversubscribed $43 million early-stage funding round to accelerate development of AI infrastructure silicon. The round was led by Matter Venture Partners with participation from Viola Ventures, GHOVC, Egis Technology and strategic investors across the global semiconductor and AI infrastructure ecosystem.
TYLsemi is positioning itself as the first pure-play chiplet company to deliver a full portfolio spanning IO connectivity, power delivery and memory alongside end-to-end custom silicon design, integration and supply-chain ownership—a combination the company says can reduce custom AI silicon development time and cost by up to 50% from architecture to high-volume manufacturing.
The company was co-founded by Mohit Gupta and Sunil Bhardwaj, industry veterans who have led engineering and operations teams at Alphawave (acquired by Qualcomm), SiFive, Cadence Design Systems and Rambus. Their thesis is that AI systems are rapidly moving from monolithic chip designs to distributed, multi-die architectures as chip sizes approach physical limits and connectivity and power become system-level bottlenecks. Advances in packaging technologies and the emergence of standardized interconnects such as UCIe have made chiplet-based design practical at scale, yet no dedicated chiplet company has served this market with a full, pre-validated, production-ready portfolio—until TYLsemi.
TYLsemi’s initial product portfolio spans four offerings. TYL.IO is a versatile family of connectivity chiplets enabling high-bandwidth, standards-based connectivity across high-performance AI systems, supporting PCIe, ESUN and UALink today with a co-packaged optics roadmap for next-generation rack-scale fabrics. TYL.Power is an integrated voltage regulator chiplet that provides efficient, intelligent in-package power delivery and optimized system-level power efficiency for XPUs. TYL.Mem is a planned memory connectivity product family for advanced AI systems, with additional details to be announced as the roadmap progresses. TYL.Forge is a full-stack platform for customer-defined XPU, compute and fabric designs, implemented using TYLsemi’s connectivity and power delivery portfolio alongside IP, foundry, packaging and production readiness services. TYL.IO and TYL.Power chiplet samples will be available to qualified customers in 2027 in partnership with TSMC; TYLsemi is now engaging lead customers for its TYL.Forge platform.
The commercial opportunity TYLsemi is targeting is substantial. The AI accelerator market is projected to reach $604 billion by 2033, with custom silicon XPUs built for specific hyperscaler workloads as the fastest-growing segment. At that scale, chiplet-based design is increasingly necessary as no single die can economically integrate all the compute, connectivity, power and memory functions required by modern AI systems. By offering pre-validated, standards-based chiplets as reusable building blocks, TYLsemi aims to make advanced custom silicon development accessible not only to hyperscalers with large internal teams but also to emerging AI companies and mid-tier infrastructure players that could not previously afford the cost and timeline of full custom design.
Tier-1 customer engagements are described as validating technology readiness and market opportunity, and strategic investor Egis Technology—whose Mobius100 datacenter-grade compute CPU is being developed on 3nm-class process technology—highlights TYLsemi’s IO and integrated voltage regulator chiplets as highly complementary to its own roadmap for modular, power-efficient AI infrastructure platforms.
KEY QUOTES:
“The AI accelerator market is on track to reach $604 billion by 2033 and custom silicon XPUs built for specific hyperscaler workloads are the fastest-growing segment. At that scale, chiplet-based design is no longer optional, yet there is no pure-play chiplet company serving this market with a full portfolio. TYLsemi closes that gap with standards-based chiplets combined with UCIe-based die-to-die connectivity, XPU-aware design, packaging, and integration — giving customers a fast, proven path to AI-era silicon.”
Mohit Gupta, Founder and CEO, TYLsemi
“AI infrastructure is entering an era of rapid scaling, so the ability to develop advanced silicon quickly and efficiently will be a defining advantage. TYLsemi is building foundational chiplet technologies for custom silicon that will make the design process faster, less risky, and more accessible, unlocking significant value and velocity across the AI ecosystem.”
Wen Hsieh, Founding Managing Partner, Matter Venture Partners
“TYLsemi has built the chiplet platform the entire AI silicon industry needs — one that can serve the scale of a hyperscaler and the speed requirements of an emerging AI company in the same breath. For the first time, advanced custom silicon development isn’t a competitive moat reserved for the largest players; it’s a platform.”
Zvika Orron, Managing Partner, Viola Ventures
“TYLsemi’s standards-based chiplets democratize chip development for startups and large silicon and system developers at a much lower cost. This enables them to develop multiple chip generations in parallel to deliver custom silicon at a much faster pace.”
Shri Dodani, Founder and Managing Partner, GHOVC
“As Egis advances Mobius100, our datacenter-grade compute CPU based on a leading compute architecture and 3nm class process technologies, we see chiplet-based IO, memory, and intelligent power delivery as essential building blocks for next-generation AI infrastructure. TYLsemi’s standards-based chiplet platform, including IO and IVR chiplets, is highly complementary to our roadmap, and we look forward to exploring opportunities to integrate these technologies into future modular, power-efficient AI infrastructure platforms.”
Steve Lo, Chairman, Egis Technology
